1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
In a semiconductor device such as LSI, a number of MOS transistors are integrally formed on a semiconductor substrate. However, it is rare that operating voltages of all the MOS transistors are the same. In general, MOS transistors each operating at a high voltage (high-voltage MOS transistors) and MOS transistors each operating at a low operating voltage (low-voltage MOS transistors) are embedded in the silicon substrate.
As an example of such a semiconductor device, FIG. 1 shows a configuration diagram of a semiconductor device in which a non-volatile memory and logic circuits are embedded.
As shown in FIG. 1, in this semiconductor device, a plurality of flash memory cells FL are formed in a cell region 1 as non-volatile memory cells. In addition, around this cell region 1, a row selection circuit 2, a column selection circuit 3, a sense amplifier 4, and a booster circuit 5 are formed as logic circuits. Then, each of the memory cells FL is selected by one of word lines WLi (i=1, 2, . . . ) each connected to the row selection circuit 2 and one of bit lines BLj (j=1, 2, . . . ) each connected to the column selection circuit 3.
Programming of each memory cell is done by applying high voltage such as 5V to a BL selected by the column selection circuit 3 and applying high voltage such as 9V to a WL selected by the row selection circuit 2.
On the other hand, erasing of memory cells is done by applying high voltage such as 10V to substrate and applying high voltage such as −10V to WL. At that time, the applied high voltage such as 10V to substrate is also applied to all BL through forward biased drain junction.
Thus, both row and column selection circuits 2 and 3 are formed of high voltage transistors.
In contrast, the sense amplifier 4, which reads information from each of the cells, is formed of low-voltage MOS transistors operating at a low voltage of approximately 1.2V.
In this manner, the semiconductor device in which the non-volatile memory and the logic circuits are embedded has a configuration in which the high-voltage transistors and the low-voltage transistors are embedded.
FIG. 2 shows a more detailed configuration diagram of the above-described semiconductor device. An example of FIG. 2 shows a state in which flash memory cells FL1 and FL3 are unselected and in which a flash memory cell FL 2 is selected.
FIG. 3 is a cross-sectional view of a semiconductor device in which high-voltage transistors and low-voltage transistors are mounted as described above.
In an example of FIG. 3, transistor formation regions are defined in a p-type silicon substrate 10 by element isolation insulating films 11. A first n-well 12, a p-well 13, and a second n-well 14 are formed in each of the transistor formation regions as shown in the figure.
In addition, gate electrodes 15 are formed on these wells 12 to 14 with gate insulating films interposed therebetween. Furthermore, a first p-type source/drain region 18, an n-type source/drain region 19, and a second p-type source/drain region 17 are formed respectively beside the gate electrodes 15.
Thus, a low-voltage p-type MOS transistor TRp(low), a low-voltage n-type MOS transistor TRn(low), and a high-voltage p-type MOS transistor TRp(high) are constructed respectively of pairs of the gate electrodes 15 and the corresponding source/drain regions 17 to 19.
In the high-voltage p-type MOS transistor TRp(high), a high-voltage is applied to the second p-type source/drain region 17. For this reason, punch through is easily generated between the second p-type source/drain region 17 and the p-type silicon substrate 10.
The punch through is often observed in the case where the second n-well 14 is shallow.
Therefore, in general the second n-well 14 is formed deeply.
In contrast, if the first n-well 12 and the p-well 13, in which the low-voltage MOS transistors TRp(low) and TRn(low) are formed respectively, are formed deeply, impurities in the respective wells spread in lateral directions. This makes it difficult to shorten the distance between, for example, the first p-type source/drain region 18 and n-type source/drain region 19. Thereby, this causes a problem that it is difficult to downsize a semiconductor device. For this reason, the first n-well 12 and the p-well 13 are generally formed to be shallower than the second n-well 14.
However, if the wells 12 and 13 used for the low-voltage transistors are shallower than the well 14 used for the high-voltage transistor, a parasitic NPN bipolar transistor formed along a path P as shown in FIG. 3 becomes critical.
FIG. 4 is a diagram showing a height of a potential for electrons along the path P in the case where both of the p-type silicon substrate 10 and the first n-well 12 are set at a ground potential (0V), and a high-voltage (10V) is applied to the second n-well 14.
As shown in FIG. 4, a height V of the potential barrier formed between the first n-well 12 and the substrate 10 is made to be lowered, because impurity concentration of the p-type silicon substrate 10, functioned as a base of the parasitic NPN bipolar transistor, is low. Accordingly, even when only a small base current IB flows, the electrons in the substrate 10 decrease. Thus, the potential becomes low as shown by the dotted line, thereby causing a large collector current IC to flow from the second n-well 14 to the first n-well 12.
As a result, a current amplification factor β (=IC/IB) of the NPN bipolar transistor becomes extremely large, thereby making latch-up easily occur. The latch-up is a phenomenon in which an excessive current flows between the n-wells 12 and 14 through the path P.
Such a problem also occurs in a semiconductor device having a cross-sectional structure shown in FIG. 5.
This semiconductor device is formed by making the first n-well 12 deeper than that in the example of FIG. 4, and by forming a high-voltage p-type MOS transistor TRp(high) on the well 12. Other than this, the semiconductor device has the configuration same as that of the example of FIG. 4.
In this semiconductor device, there is also a problem in that latch-up along the path P easily occurs due to the reason same as that described in FIG. 4.
In Specification of Japanese Patent No. 3564039 and Specification of Japanese Patent No. 3117428, it is disclosed that latch-up can be suppressed by forming, at end portions of each of the wells, high-concentration impurity layers each having the conductive type same as that of the well.
A structure shown in FIG. 6 is obtained by applying such high-concentration impurity layers to the semiconductor device of FIG. 5.
As shown in FIG. 6, in this example, in line with Specification of Japanese Patent No. 3564039 and Specification of Japanese Patent No. 3117428, n-type high-concentration impurity layers 12a and 14a, and p-type high-concentration impurity layers 13a are formed at end portions of the respective wells 12 to 14.
However, even when such high-concentration impurity layers 12a to 14a are formed, a base concentration of the NPN parasitic bipolar transistor is not changed and stays equal to that of the case of FIG. 5. Therefore, a height of the potential for the electrons along the path P remains low. For this reason, latch-up still easily occurs along the path P.
In addition to these, a technology relating to the present invention is also disclosed in Official Gazette of Japanese Patent Application No. 2003-273236.